The present invention generally relates to clock generator circuits, and, more particularly, to a diagnostic circuit in a clock generator circuit.
Integrated circuits (ICs) include various internal circuit modules and circuitry such as data converters, processors, flip-flops, and latches. The circuits and modules exchange signals such as control and data signals. For proper operation, the exchange of signals must be synchronized. Hence, the IC includes a clock generator circuit that generates clock signals to synchronize the exchange of signals. In some cases, an external clock generator may be connected to the IC to generate and provide the clock signals.
Conventional clock generator circuits include an oscillator circuit such as a Pierce crystal oscillator circuit, a Wien bridge oscillator circuit, and a Colpitts oscillator circuit. Such oscillator circuits include an oscillation source such as a piezoelectric crystal for generating an oscillating signal and an amplifier for receiving the oscillating signal and generating an amplified signal. The clock generator circuits further include a shaping circuit such as a Schmitt trigger or a comparator for receiving the amplified signal and generating a clock signal.
For proper operation, the clock signal must be stable and parameters of the characteristics of the clock signal such as duty cycle, frequency, and amplitude must be greater than their respective threshold values. Hence, to ensure that the parameters of the clock signal exceed the respective threshold values, the clock generator circuit includes a counter to count up to a predetermined value before generating a clock ready signal. This predetermined count value ensures that sufficient time is provided for the clock generator circuit to generate a stable clock signal.
However, for a given resonant frequency of the oscillating signal, the time required for the parameters of the clock signal to exceed their respective threshold values varies due to on-chip variations (OCV) such as process, voltage, and temperature (PVT) variations, as well as board parasitics. Hence, the predetermined count value is selected such that the parameters of the clock signal exceed the respective threshold values even under worst-case PVT conditions. Thus, the clock ready signal is generated after a predetermined time period even though the parameters of the clock signal may exceed their respective threshold values before the predetermined time period, thereby resulting in a long start-up time.
A known technique to improve the start-up time is to use a diagnostic circuit. FIG. 1 is a schematic block diagram of a conventional clock generator circuit 100. The clock generator circuit 100 includes an oscillator circuit 102, a shaping circuit 104, and a diagnostic circuit 106. The oscillator circuit 102 may be a Pierce crystal oscillator circuit and include a first amplifier circuit 108, a first oscillation source 110, a first resistor 112, and first and second capacitors 114 and 116. The first oscillation source 110 is a piezoelectric crystal and the first amplifier circuit 108 is an inverting amplifier circuit.
The first oscillation source 110 is connected between input and output terminals of the first amplifier circuit 108. The first oscillation source 110 generates a first oscillating signal (VOSC_1). The first amplifier circuit 108 receives the first oscillating signal (VOSC_1) at its input terminal and generates a first amplified signal (VAMP_1) at its output terminal.
The first resistor 112 is connected between the input and output terminals of the first amplifier circuit 108 and provides a direct current (DC) operation bias of the first amplifier circuit 108.
The first capacitor 114 is connected between the input terminal of the first amplifier circuit 108 and ground. The second capacitor 116 is connected between the output terminal of the first amplifier circuit 108 and ground. The first and second capacitors 114 and 116 are selected such that the first oscillation source 110 has a parallel resonant frequency close to its series resonant frequency. The first amplifier circuit 108 generates the first amplified signal (VAMP_1) at a frequency that is between the series and parallel resonant frequencies of the first oscillation source 110. The first amplifier circuit 108, and the first oscillation source 110 and the first and second capacitors 114 and 116 cause the first amplified signal (VAMP_1) to undergo a phase shift that is a multiple of 360 degrees.
The shaping circuit 104 comprises a first Schmitt trigger and is connected to the output terminal of the first amplifier circuit 108 for receiving the first amplified signal (VAMP_1) and generating an intermediate clock signal (VINT_CLK).
The diagnostic circuit 106 includes a hysteresis circuit 118 and an AND gate 120. The hysteresis circuit 118 has a hysteresis voltage greater than a hysteresis voltage of the shaping circuit 104. The hysteresis circuit 118 is connected to the output terminal of the first amplifier circuit 108 for receiving the first amplified signal (VAMP_1) and generating a clock ready signal (VCLK_RDY). The hysteresis circuit 118 generates a high clock ready signal (VCLK_RDY) when the amplitude of the first amplified signal (VAMP_1) is greater than a first threshold value or less than a second threshold value. For example, the first threshold value may be 75% of a full swing voltage and the second threshold value may be 25% of the full swing voltage.
The AND gate 120 has first and second input terminals connected to the shaping circuit 104 and the hysteresis circuit 118 for receiving the intermediate clock signal (VCLK_INT) and the clock ready signal (VCLK_RDY), respectively. The AND gate 120 has an output terminal for generating a first clock signal (VCLK_1). The AND gate 120 generates the first clock signal (VCLK_1) signal only when the hysteresis circuit 118 enables the clock ready signal (VCLK_RDY). Thus, the first clock generator circuit 100 provides the first clock signal (VCLK_1) when the clock ready signal (VCLK_RDY) is enabled by the hysteresis circuit 118.
The diagnostic circuit 106 determines whether the amplitude of the first amplified signal (VAMP_1) is greater than the first threshold value or less than the second threshold values. However, the diagnostic circuit 106 does not determine whether the duty cycle of the intermediate clock signal (VINT_CLK) is within respective predefined threshold values. Thus, the duty cycle of the intermediate clock signal (VINT_CLK) may not lie within respective predefined threshold values and hence, the duty cycle of the first clock signal (VCLK_1) also may not be within respective predefined threshold values. Further, the common mode voltage of the first amplified signal (VAMP_1) varies with properties of the first oscillation source 110 and also due to PVT variations. Therefore, the hysteresis circuit 118 does not efficiently adjust the clock ready signal (VCLK_RDY) per the variations in the common mode voltage of the first amplified signal (VAMP_1). Hence, the above technique may not provide the first clock signal (VCLK_1) with the parameters such as duty cycle within the required limits.
FIG. 2 is a schematic block diagram of another conventional clock generator circuit 200. The clock generator circuit 200 generates a stable clock signal with a fast start-up time. The second clock generator circuit 200 includes an oscillator circuit 202, second and third Schmitt triggers 204 and 206, and amplifier switch logic 208.
The oscillator circuit 202 includes second, third, and fourth amplifier circuits 210, 212, and 214, a second oscillation source 216, a second resistor 218, and third and fourth capacitors 220 and 222. The second amplifier circuit 210, the second oscillation source 216, the second resistor 218, and the third and fourth capacitors 220 and 220 form a Pierce crystal oscillator circuit that is structurally and functionally similar to the first oscillator circuit 102. The second, third, and fourth amplifier circuits 210, 212, and 214 are inverting amplifier circuits. The third and fourth amplifier circuits 212 and 214 have input and output terminals connected to input and output terminals of the second amplifier circuit 210. The second, third, and fourth amplifier circuits 210, 212, and 214 form an amplifier set 224. The amplifier set 224 acts as an amplifier circuit having an amplification factor equal to the sum of amplification factors of the second, third, and fourth amplifier circuits 210, 212, and 214.
The second oscillation source 216 generates a second oscillating signal (VOSC_2). The amplifier set 224 is connected to the second oscillation source 216 for receiving the second oscillating signal (VOSC_2) and generating a second amplified signal (VAMP_2).
The second Schmitt trigger 204 is connected to the amplifier set 224 for receiving the second amplified signal (VAMP_2) and generating an intermediate signal (VINT) that is indicative of the amplitude of a second clock signal (VCLK_2). The second Schmitt trigger 204 has a first hysteresis voltage.
The third Schmitt trigger 206 is connected to the amplifier set 224 for receiving the second amplified signal (VAMP_2) and generating the second clock signal (VCLK_2). The third Schmitt trigger 206 has a second hysteresis voltage that is less than the first hysteresis voltage.
The amplifier switch logic 208 is connected to the second Schmitt trigger 204 for receiving the intermediate signal (VINT). The amplifier switch logic 208 generates and provides first, second, and third switch signals (VSW_1, VSW_2, and VSW_3, respectively) to the second, third, and fourth amplifier circuits 210, 212, and 214. The first, second, and third switch signals (VSW_1, VSW_2, and VSW_3, respectively) are indicative of switching on or switching off the second, third, and fourth amplifier circuits 210, 212, and 214, respectively. For example, the first, second, and third switch signals (VSW_1, VSW_2, and VSW_3, respectively) may be enabled to switch off the second, third, and fourth amplifier circuits 210, 212, and 214, respectively, while the first, second, and third switch signals (VSW_1, VSW_2, and VSW_3, respectively) may be disabled to switch on the second, third, and fourth amplifier circuits 210, 212, and 214, respectively. In FIG. 2, the amplifier switch logic 208 is an N-bit counter that counts the pulses of the intermediate signal (VINT).
When the power to the second clock generator circuit 200 is applied, the second, third, and fourth amplifier circuits 210, 212, and 214 are switched on, thereby increasing the amplitude of the second amplified signal (VAMP_2) in a short period of time. As the voltage level of the second amplified signal (VAMP_2) is greater than the second hysteresis voltage, the third Schmitt trigger 206 generates and provides the second clock signal (VCLK_2) to electronic circuits of an IC connected to the second clock generator circuit 200. Thus, the amplifier set 224 helps in achieving a fast start-up time.
The amplifier switch logic 208 counts the pulses of the intermediate signal (VINT) and switches off one amplifier circuit of the amplifier set 224 each time the amplifier switch logic 208 counts up to a pre-determined count value, thereby reducing the amplification factor of the amplifier set 224. The amplifier switch logic 208 switches off the amplifier circuits of the amplifier set 224 one by one until only the second amplifier circuit 210 is on. When only the second amplifier circuit 210 is on, the amplification provided by the amplifier set 224 is not sufficient for the voltage level of the intermediate signal (VINT) to be greater than the voltage level of the first hysteresis voltage. Hence, the second Schmitt trigger 204 does not generate the intermediate signal (VINT) as an oscillating signal so the counting operation performed by the amplifier switch logic 208 is stopped. Thus, the logic states of the first, second, and third switch signals (VSW_1, VSW_2, and VSW_3, respectively) do not change. However, the amplification provided by the second amplifier circuit 210 is sufficient for the third Schmitt trigger 206 to generate and provide the second clock signal (VCLK_2) to the electronic circuits of the IC.
The second, third, and fourth amplifier circuits 210, 212, and 214 are switched on, when power to the clock generator circuit 200 is applied, thereby leading to power overhead. Further, the clock generator circuit 200 requires multiple amplifier circuits, two Schmitt triggers, and the amplifier switch logic for proper operation, which leads to area overhead. Furthermore, the common mode voltage of the second amplified signal (VAMP_2) varies with the properties of the second oscillation source 216 and also varies with PVT variations so the second and third Schmitt triggers 204 and 206 do not perform efficiently at all common mode voltages of the second amplified signal (VAMP_2). Also, the clock generator circuit 200 does not determine whether the duty cycle of the second clock signal (VCLK_2) is within required limits and hence, the second clock generator circuit 200 may provide an unstable second clock signal (VCLK_2) to the electronic circuits of the IC.
Therefore, it would be advantageous to have a clock generator circuit that provides a stable clock signal in a reduced time without impacting area and power overhead.